hackin-breakin-risc-v

This repository is a hacking playground for my RISC-V exploration.

We will learn about the many elements in an assembly language program. Among these elements, we have directives, labels, mnemonics, operands, immediates, instructions, and pseudo instructions. Major focus on:

Describe the RISC-V assembly language syntax and features.
Identify the many elements of a RISC-V assembly program, like directives, labels, mnemonics, and operands.
Identify the pseudoinstructions in a RISC-V assembly program.
Explain how Control and Status Registers are managed in the RISC-V assembly code.
Use immediate values properly in a RISC-V assembly program.

ARCHITECTURE

32 bit

64 bit

128 bit

REGISTERS

33 registers including $pc, 32 general use

x0-x32 + pc

RISC V instruction set

Three register instruction structure

<operation> <dst>,<src1>,<src2>
$a2= $zero +64

$a2= 64
a1= <address of helloworld label>

https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf

RISC-V SYSCALL table

Unix implementation syscall table: https://github.com/westerndigitalcorporation/RISC-V-Linux/blob/13cb16d5e8e11ebca490cad50cc5abbd222839a1/linux/include/uapi/asm-generic/unistd.h